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There are three types of modeling in verilog, each one corresponding to a different level of abstraction.
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Gate-level model |
Dataflow model |
Behavioral model |
module first_module( input a, input b, output out ); and and_gate(out,a,b); endmodule |
module first_module( input a, input b, output out ); assign out = a & b; endmodule |
module first_module( input a, input b, output out ); always @(a, b) begin out = a & b; end endmodule |
//------------------------------------------------------- //one-bit full adder module //------------------------------------------------------- module fadder( input a, //data in a input b, //data in b input cin, //carry in output sum_out, //sum output output c_out //carry output ); wire c1, c2, c3; // wiring needed assign sum_out = a ^ b ^ cin; // half adder (XOR gate) assign c1 = a & cin; // carry condition 1 assign c2 = b & cin; // carry condition 1 assign c3 = a & b; // carry condition 1 assign c_out = (c1 + c2 + c3); endmodule |
//-------------------------------------------------------
// 4x1 MUX with 1-bit inputs
//-------------------------------------------------------
module mux_4to1_case (
input a,
input b,
input c,
input d,
input [1:0] sel, // 2-bit selector
output reg out);
always @(*) begin
case (sel)
2'b00: out <= a;
2'b01: out <= b;
2'b10: out <= c;
2'b11: out <= d;
endcase
end
endmodule
//-------------------------------------------------------
// 4x1 MUX with 4-bit inputs
//-------------------------------------------------------
module mux_4to1_case (
input [3:0] a, // 4-bit input
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [1:0] sel, // 2-bit selector
output reg [3:0] out);
always @(*) begin
case (sel)
2'b00: out <= a;
2'b01: out <= b;
2'b10: out <= c;
2'b11: out <= d;
endcase
end
endmodule
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//-------------------------------------------------------
// 3 to 8 decoder
//-------------------------------------------------------
module decoder_3_to_8(output [7:0] F,
input [2:0] ABC);
assign F =(ABC == 3'b000) ? 8'b0000_0001:
(ABC == 3'b001) ? 8'b0000_0010:
(ABC == 3'b010) ? 8'b0000_0100:
(ABC == 3'b011) ? 8'b0000_1000:
(ABC == 3'b100) ? 8'b0001_0000:
(ABC == 3'b101) ? 8'b0010_0000:
(ABC == 3'b110) ? 8'b0100_0000:
(ABC == 3'b111) ? 8'b1000_0000:
8'bxxxx_xxxx;
endmodule
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//-------------------------------------------------------
// 7-segment decoder (decimal)
//-------------------------------------------------------
module decoder_ssd_dec(output [6:0] SSD,
input [3:0] IN);
assign SSD = (IN == 4'b0000) ? 7'b1111110:
(IN == 4'b0001) ? 7'b0110000:
(IN == 4'b0010) ? 7'b1101101:
(IN == 4'b0011) ? 7'b1111001:
(IN == 4'b0100) ? 7'b0110011:
(IN == 4'b0101) ? 7'b1011011:
(IN == 4'b0110) ? 7'b1011111:
(IN == 4'b0111) ? 7'b1110000:
(IN == 4'b1000) ? 7'b1111111:
(IN == 4'b1001) ? 7'b1111011:
7'bXXXXXXX; // Don't cares
endmodule
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//-------------------------------------------------------
// 7-segment decoder (hexadecimal)
//-------------------------------------------------------
module decoder_ssd_hex(output [6:0] SSD,
input [3:0] IN);
assign SSD = (IN == 4'b0000) ? 7'b1111110:
(IN == 4'b0001) ? 7'b0110000:
(IN == 4'b0010) ? 7'b1101101:
(IN == 4'b0011) ? 7'b1111001:
(IN == 4'b0100) ? 7'b0110011:
(IN == 4'b0101) ? 7'b1011011:
(IN == 4'b0110) ? 7'b1011111:
(IN == 4'b0111) ? 7'b1110000:
(IN == 4'b1000) ? 7'b1111111:
(IN == 4'b1001) ? 7'b1111011:
(IN == 4'b1010) ? 7'b1110111:
(IN == 4'b1011) ? 7'b0011111:
(IN == 4'b1100) ? 7'b0001101:
(IN == 4'b1101) ? 7'b0111101:
(IN == 4'b1110) ? 7'b1001111:
(IN == 4'b1111) ? 7'b1000111:
7'bXXXXXXX; // Don't cares
endmodule
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