Flip-flop

Verilog Description

D Flip-flop

module dff (q,d,clk)
    output reg q;
    input d, clk;
    
    always @(posedge clk)
        q <= d;
            
endmodule

      

D Flip-flop with Asynchronous reset

module dff (q,d,clk,reset)
    input d,clk,reset;
    output q;
    reg q;
    
    always @(posedge clk or negedge reset)
        if (reset)
            q <= 1'b0;
        else
            q <= d;
            
endmodule
      

JK Flip-flop

module jk_ff (j,k,clk,q);  
   
   input j,k,clk;
   output reg q;
  
   always @ (posedge clk)  
      case ({j,k})  
         2'b00 :  q <= q;  
         2'b01 :  q <= 1'b0;  
         2'b10 :  q <= 1'b1;  
         2'b11 :  q <= ~q;  
      endcase  
endmodule
      

JK Flip-flop with Asynchronous reset

module jk_ff (j,k,clk,reset,q);

    input j,k,clk,reset;
    output reg q;
  
    always @ (posedge clk or negedge reset)  
        if (reset == 1'b0) begin
            q <= 1'b0;
        end
        else begin
            case ({j,k})  
                2'b00 :  q <= q;  
                2'b01 :  q <= 1'b0;  
                2'b10 :  q <= 1'b1;  
                2'b11 :  q <= ~q;
            endcase
        end
endmodule